1. Field of the Invention
The present invention relates to a clock signal switching circuit which switches between clock signals having different frequencies to select a suitable clock signal for operating IC cards, for use in, for instance, IC card reader/writers.
2. Description of the Related Art
Although IC cards in which CPUs and memories are housed are frequently used as prepaid cards, there are still some portions which are not standardized. For instance, there by be two clock frequencies to operate the CPU, 4.9152 MHz and 3.579545 MHz. For this reason, clock oscillator circuits for each of the above two frequencies are provided in the reader/writers used for writing and reading information for IC cards. After an IC card has been inserted into the reader/writer, they first carry out a check to find out which operating clock frequency is being used, and then operate the CPU in the IC card using the correct clock frequency.
The clock signal switching circuit is used to determine which clock frequency to use, and, then to switch to a clock of the correct frequency. For the construction of such a circuit, the one shown in FIG. 1, for instance, could be considered.
In FIG. 1, a numeral 1 denotes an input terminal for a first clock signal of 4.9152 MHz (hereafter called "the f.sub.1 clock signal"), a numeral 2 denotes an input terminal for a second clock signal of 3.579545 MHz (hereafter called "the f.sub.2 clock signal"), and a numeral 3 denotes an input terminal for a frequency switching signal (hereafter called simply "the switching signal"). The f.sub.1 clock signal input terminal 1 and switching signal input terminal 3 are connected to the input terminals of a first NAND gate 4. The f.sub.2 clock signal input terminals is connected to one of the input terminal of a second NAND gate 5 and the switching signal input terminal 3 is connected to the other input terminal of the second NAND gate 5 via an inverter 6. Also, the output terminals of the first and second NAND gates 4 and 5 are each connected to respective input terminals of a third NAND gate 7. Either the f.sub.1 clock signal or f.sub.2 clock signal is output by the output terminal of the third NAND gate 7.
FIG. 2 shows a timing chart for each signal in the above clock signal switching circuit. In FIG. 2 (a) shows the f.sub.1 clock signal, (b) shows the f.sub.2 clock signal, and (c) shows the switching signal. The switching signal (c) is composed a signal which varies between the two levels of an H level and an L level. When the switching signal (c) is at the H level, first NAND gate 4 opens and the f.sub.1 clock signal (a) is output from its output terminal. At the same time, second NAND gate 5 closes and its output becomes the H level, and thus the f.sub.1 clock signal is output from third NAND gate 7.
When the switching signal (c) switches from the H level to the L level during the output of the f.sub.1 clock signal, the first NAND gate 4 immediately closes and its output becomes H level as shown by (d) in FIG. 2. At the same time, second NAND gate 5 opens and the f.sub.2 clock signal (b) is output from its output terminal as shown by (e) in FIG. 2, and thus the f.sub.2 clock signal (b) is output from third NAND gate 7 by switching as shown by (f) in FIG. 2. When the switching signal (c) switches from the L level to the H level during the output of the f.sub.2 clock signal (b), first NAND gate 4 immediately opens and second NAND gate 5 closes. Thus the circuit returns to the previous state and the f.sub.1 clock signal (a) is output from third NAND gate 7 by switching.
As described above, the prior art clock signal switching circuit was designed so that when the switching signal switched from the H level to the L level, or vice versa, first NAND gate 4 and second NAND gate 5 immediately opened or closed and thus the f.sub.1 clock signal or the f.sub.2 clock signal were immediately output from third NAND gate 7. For this reason, as shown by the (*) signs in FIG. 2(f), a variable portion of clock width which differed from the clock width of either the f.sub.1 clock signal (a) or the f.sub.2 clock signal (b) occured during the switching between the f.sub.1 clock signal and the f.sub.2 clock signal, depending on the timing of the switching. Consequently, there was a risk of malfunction occurring in the CPU of an IC card with this type of clock. Therefore, when switching of the clock signal in an IC card reader/writer required, the IC card was temporarily reset by a reset signal as shown by (g) in FIG. 2. Then, after the clock frequency had been switched, the IC card was started by releasing this reset. However, executing this type of reset operation, led to an increase in the load on the software and, at the same time, led to increased processing time.